1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming isolated germanium-containing fins for a FinFET semiconductor device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A conventional FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed and in lowering operation currents and voltages of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a FinFET device 10. In this example, the FinFET device 10 includes three illustrative fins 14, a gate structure 16, sidewall spacers 18 and a gate cap layer 20. The gate structure 16 is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 10. The fins 14 have a three-dimensional configuration: a height 14H, a width 14W and a long-axis or axial length 14L. The axial length 14L corresponds to the direction of current travel in the device 10 when it is operational. The dashed line 14C depicts the long-axis or centerline of the fins 14. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. In a conventional process flow, the portions of the fins 14 that are positioned outside of the spacers 18, i.e., in the source/drain regions of the device 10, may be increased in size or even merged together (a situation not shown in FIG. 1) by performing one or more epitaxial growth processes. The process of increasing the size of or merging the fins 14 in the source/drain regions of the device 10 is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions. Even if an epi “merge” process is not performed, an epi growth process will typically be performed on the fins 14 to increase their physical size.
In the FinFET device 10, the gate structure 16 may enclose both sides and the upper surface of all or a portion of the fins 14 to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer (not shown), e.g., silicon nitride, is positioned on the top surface of the fins 14 and the FinFET device 10 only has a dual-gate structure (sidewalls only). Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins 14, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device, the “channel-width” is estimated to be about two times (2x) the vertical fin-height 14H of the fin 14 plus the width of the top surface of the fin 14, i.e., the fin width 14W. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFET devices tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond. The gate structures 16 for such FinFET devices 10 may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
However, FinFET devices still exhibit some performance-limiting characteristics. As noted above, one such characteristic that is detrimental to all forms of semiconductor devices, both FinFETs and planar FETs, is off-state leakage currents. Ideally, off-state leakage current is minimized to increase device performance. In the case of a FinFET device, it has been noted that the so-called “punch through leakage current” densities vary along the vertical length of the fins, with the current densities being much greater at the bottom of the fins proximate the local isolation regions of the device. See, e.g., Okano et al., “Process Integration Technology and Device Characteristics of CMOS FinFET on Bulk Silicon Substrate with sub-10 nm Fin Width and 20 nm Gate Length,” IEDM Technical Digest, pp. 721-724, 2005. Efforts have been made in the past in attempts to reduce such punch through leakage currents in FinFET devices. However, as device dimensions continue to shrink, better and more efficient techniques are desired in an effort to eliminate or reduce detrimental leakage currents.
The present disclosure is directed to various methods of forming isolated germanium-containing fins for a FinFET semiconductor device that may solve or reduce one or more of the problems identified above.